In the field of electronic systems, the use of gate arrays to implement digital functions has become widespread in recent years. As is well known in the art, a gate array is an integrated circuit fabricated as a regular arrangement of transistors, which can be interconnected according to the desired digital function. The transistors are conventionally grouped into "base cells", rather than as individual transistors, with each base cell comprising a sufficient number of transistors to implement an elemental logic function (i.e., a "gate"). A base cell (often also referred to as a "basic cell", "basic block", or "functional block") corresponds to a step-and-repeat silicon structure, from which a circuit function is realized by the routing of overlying metal or other conductive elements.
The use of gate arrays allows for the rapid production of customized digital circuits. This results from the fabrication of integrated circuit wafers with the transistors in the base cells defined by lower level physical elements, but with the actual digital circuit function not defined until later stages in the manufacturing process. In the case of MOS gate arrays, the base cell transistors are defined by source and drain diffusions and first level polysilicon gate electrodes. Upper level metal interconnections are then defined to interconnect the transistor elements according to the desired circuit function. This process allows the customized arrangement of the gates, or cells, to be implemented at the latest stages in the manufacturing process, reducing the design-to-manufacture time of the digital circuit. Custom integrated circuits may thus be produced at very short cycle times, and with a minimum number of custom photomasks.
The cost of gate array implementations, as is the case with other integrated circuits, depends upon the amount of semiconductor area used to implement the function, and also upon the complexity of the manufacturing process. Accordingly, the ability to utilize a high percentage of the base cells in a circuit results in a low cost implementation of the function, as high utilization enables the realization of a complex digital function in relatively little semiconductor area. Multiple levels of interconnection may be used to increase the cell utilization by allowing metal conductors to cross-over one another, but the manufacturing cost increases dramatically as additional interconnection layers are introduced. The gate array designer is therefore often faced with a tradeoff between the utilization rate of the available cells and the number of interconnection levels to be used.
Another concern for the gate array designer is to provide isolation between cells or transistors within the gate array, as such isolation is of course necessary to ensure proper circuit function. As in the case with any integrated circuit of the MOS type, isolation may be implemented by transistors biased into an off condition, by physical barriers such as oxide structures, or by a combination of the two (the well-known field oxide transistors). Selection of the isolation technique and its interaction with the elements of the base cell are significant factors that affect the efficiency of the gate array.
Other design rules, such as the minimum channel length and width of the transistors to provide the specified drive capability in combination with the process technology used, and such as the spacing requirements between elements of the same or different levels, must also be considered in the design of the gate array base cell.
Referring now to FIGS. 1a and 1b, a first conventional gate array base cell will be described for purposes of background. Cell 2 of FIGS. 1a and 1b is implemented according to the cutoff transistor isolation type, as will be apparent from the description below, and according to complementary metal-oxide-semiconductor (CMOS) technology. Conventional cell 2 in this example includes a p-channel transistor and an n-channel transistor, and as such the elemental gate implemented by cell 2 is a CMOS inverter.
Referring to FIG. 1a, each cell 2 includes polysilicon electrode 10 and polysilicon electrode 12, each of which have enlarged pad regions at their terminal ends which overlie field oxide 4. The p-channel transistor in cell 2 is implemented by polysilicon electrode 10 which is disposed between (and overlies) p-type diffused regions 6 in the conventional manner for PMOS transistors, such that the p-type diffused region 6 on either side of electrode 10 serve as the source and drain regions for the p-channel transistor with electrode 10 serving as the gate for the transistor. Similarly, electrode 12 in cell 2 is disposed between and above n-type diffused regions 8, so that n-type diffused regions 8 may serve as source and drain, and electrode 12 as the gate, of an NMOS transistor. It is preferred that p-type diffused regions 6 and n-type diffused regions 8 are formed as diffusions performed after electrodes 10, 12 are in place, so that the transistors defined thereby are according to the well-known self-aligned configuration. Depending upon the particular conventional process used for fabrication, one or both of p-type diffused regions 6 or n-type diffused regions 8 may be formed in a well; in this example, p-type diffused regions 6 are formed in an n-type well, the boundary of which is illustrated in FIG. 1 by boundary WB. P-type diffused regions 6 are separated from n-type diffused regions 8 by field oxide 4 therebetween.
Disposed outside of field oxide 4 at the top and bottom of cell 2 (in the view of FIG. 1a) are diffused regions 7n and 7p, respectively. N-type diffused region 7n is formed in the n-well within which p-type diffused regions 6 are formed, and as such provides a location at which the bias of the n-well may be fixed (e.g., to V.sub.dd); similarly, p-type diffused region 7p is formed into the p-type material within which n-type diffused regions 8 are formed, and thus provides a location for back-biasing the NMOS transistors in cells 2. In this conventional configuration, the row of cells above cells 2 of FIG. 1a have their PMOS transistors on the bottom, so that the diffused region 7n is shared between immediately adjacent cells 2 in the vertical direction of FIG. 1a. Similar reversal of the NMOS and PMOS transistors in the row of cells below cells 2 of FIG. 1a allow for sharing of p-type diffused region 7p therebetween.
The isolation technique used in the conventional example of FIGS. 1a and 1b is the cutoff transistor type, in which an adjacent transistor to that for which the function is desired is forced into its "off" state, preventing conduction from the transistors used to perform the digital logic function. Referring to FIG. 1b, cell 2 is illustrated after formation of overlying metallization used to implement the cutoff isolation; of course, other metallization (not shown in FIG. 1b) will also be used to implement the desired function of cell 2. In FIG. 1b, metal line 14 is connected to a V.sub.dd power supply, and is connected by way of silicon contacts both to p-type diffused region 6' and to electrode 10'. As such, the transistor defined by electrode 10' is necessarily held in the "off" state, given that all voltages in the circuit are between ground and V.sub.dd. Accordingly, p-type diffused region 6" in cell 2 is isolated from p-type diffused region 6', such that p-type diffused region 6" may be driven to any voltage between V.sub.dd and ground without significant leakage to p-type diffused region 6'.
An alternative connection is illustrated relative to the n-channel transistor in FIG. 1b, as metal line 16 is connected to ground and by way of contact vias to n-type diffused region 8'; electrode 12' does not receive the ground bias in this case. As a result of metal lines 16, the transistor defined by electrode 12' may operate in combination with the n-channel transistor defined in cell 2, with a source region biased to ground.
The geometry of cell 2 in the example of FIGS. 1a and 1b is selected to provide the desired transistor drive characteristics and to accommodate a desired number of interconnection "tracks" in which metallization lines may be placed. Considering the difference in carrier mobilities, in this example the p-channel transistor width (i.e., the length of electrodes 10) is wider than that of the n-channel transistors (i.e., the length of electrodes 12). In this example, cell 2 provides eighteen metallization tracks running horizontally, with one horizonal track across each of the four rows of pads connected to electrodes 10 and 12, five tracks across the n-channel transistor area (electrodes 12), seven tracks across the p-channel transistor area (electrodes 10), one track over field oxide 4 between electrodes 10 and 12 (i.e., overlying well boundary WB in FIG. 1a), and one track for power distribution extending between rows of cells 2.
The number of interconnection tracks is selected based on the necessary number of tracks for implementation of conventional building-block gates, such as NAND, NOR, and D-type flip-flops (DFFs), that are expected to be used in most digital circuits to be implemented by the gate array with a given utilization factor and process complexity. For example, cells 2 of FIGS. 1a and 1b with eighteen tracks will yield approximately 75 to 80 percent usability (i.e., the percent of transistors to which connection may be made) if triple-level metallization is used. However, if the number of tracks is reduced to save silicon area, cross-connections or jumpers in one of the metal levels may be required, which will in turn reduce usability.
The example of FIGS. 1a and 1b is a conventional result for a cutoff isolation gate array, based on the above-noted tradeoffs. The power dissipated by the transistors is relatively high, however, given the large channel width necessary to accommodate the metallization tracks; for example, the size of cell 2 is 45 microns by 2.5 microns when using a modern fabrication process. In addition, the arrangement of cells 2 according to adjacent p-type and n-type transistors requires several cells to implement a digital function. For example, a two-input NAND function requires three cells 2 (or six transistors) for its implementation, considering the necessary isolation transistors. Accordingly, the cell arrangement of FIGS. 1a and 1b is quite efficient for circuits which utilize stacked inverters, as electrodes 10, 12 are easily connected to one another over field oxide 4 therebetween, but is relatively inefficient for certain realizations, such as transmission gate latches.
Referring now to FIG. 2, another conventional base cell arrangement utilizing oxide isolation is illustrated, and will now be described for purposes of background. Cells 20 of FIG. 2 are constructed according to CMOS technology, and as such include p-type diffused regions 26a through 26c and n-type diffused regions 28a through 28c. Each cell 20 in this example includes two electrodes 22a, 22b which extend over both the p-type transistor region and also the n-type transistor region; electrode 22a separates diffused regions 26a, 28a from diffused regions 26b, 28b, respectively, and electrode 22b separates diffused regions 26b, 28b from diffused regions 26c, 28c, respectively. According to this embodiment, therefore, p-channel and n-channel gates are connected together in each cell 20, with each cell 20 including two such gates. Electrodes 22a, 22b each have three flags or pads for connection, one at each end overlying field oxide 24, and one overlying field oxide 24 disposed between p-type diffused regions 26a, 26b, 26c and respective n-type diffused regions 28a, 28b, 28c. Diffused regions 23 are located at each end of cells 20, with n-type diffused region 23n within the n-well containing p-type diffused regions 26, and with p-type diffused region 23p within the p-well containing n-type diffused regions 28. Overlying metal power and ground bus lines (not shown) make contact to the wells by way of diffused regions 23, and thus provide substrate bias to the transistors in cell 20.
Neighboring cells 20 are isolated from one another, in the example of FIG. 2, by field oxide 24 disposed therebetween. In this example, p-type diffused region 26c is isolated from p-type diffused region 26a in the adjacent cell 20 by field oxide 24 of width d.sub.I ; similarly, n-type diffused region 28c is isolated from n-type diffused region 28a in the adjacent cell 20 by field oxide 24 of width d.sub.I. Accordingly, each cell 20 is electrically isolated from adjacent cells by field oxide, unless interconnection by way of overlying metallization (not shown) makes the desired connection.
Cells 20 of FIG. 2 in this example include both vertical and horizontal interconnection tracks (relative to FIG. 2). For each cell 20, four vertical tracks run over the three flags or pads of electrodes 22a, 22b. Ten horizontal tracks may be implemented in cells 20, with three tracks across each of the p-type diffused regions 26 and n-type diffused regions 28, one track across each of the three flags of electrodes 22a, 22b. The tenth horizontal wiring track is between cells, with half of a track over each of diffused regions 23 illustrated in FIG. 2. Adjacent cells 20 in the vertical direction to those shown in FIG. 2 will have their n-type transistors below their p-type transistors (i.e., reversed in the vertical direction from those shown in FIG. 2), so that the cell immediately below cell 20 in FIG. 2 will have its diffused region 23p at its top, shared with diffused region 23p of cell 20.
As in the case of cells 2 of FIGS. 1a and 1b, the number of tracks selected in each direction are according to the number of necessary tracks for typical gates useful in digital circuits, such as NANDs, NORs, and D-type flip-flops (DEFs). Each cell 20 according to this embodiment of the invention, while including only four transistors, is sufficient to realize a two-input NAND function, since no transistors are required for isolation between cells 20. The oxide isolation structure of cells 20 of FIG. 2 has been observed to be very efficient in realizing transmission gate latches, but very inefficient in implementation of stacked inverter type latches and similar circuits.
Comparison of the base cell architectures of FIGS. 1a and 1b, on the one hand, and FIG. 2, on the other hand, will show that each has significant advantages and disadvantages relative to the other. The relative efficiencies of implementation of stacked inverter latches and transmission gate latches have been noted above. In addition, the cutoff isolation arrangement of FIGS. 1a, 1b allows for close implementation of cells, as no oxide is necessary; the oxide isolation arrangement of FIG. 2 reduces the necessary transistor width from that of the cutoff isolation cell, and thus reduces the power dissipation of the circuit.
It is an object of the present invention, however, to provide a base cell architecture in which transistors with minimum channel width may be used in combination with cutoff isolation.
It is a further object of the present invention to provide such an architecture in which additional transistors may be utilized in lieu of cutoff isolation for complex multiple-cell gate elements.
It is a further object of the present invention to provide such an architecture in which the silicon area required for isolation is minimized.
It is a further object of the present invention to provide such an architecture that is efficient for both stacked inverter and transmission gate style latch realization.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.